职位详情:

工作地区:	上海	待遇:	面议	学历要求:	高中及以上

岗位要求:
Senior verification EngineerResponsibilities:Responsibilities will include developing verification environment; developing test plans for and verifying the function of ASIC; hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams. The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work. The candidate also needs to have a full understanding of design using Verilog and working experience with SystemVerilog. A strong communication skill in both Chinese and English is required.Qualifications:5+ years of ASIC Design verification experience, complex SOC verification experience is preferredStrong programming skills in SystemVerilogKnowledgeable in Verilog/Verilog-PLI/SystemC/SVA/C/C++Working Experience with UVM/OVM/VMM (at least one of them)Responsible for implementation of verification environment and generation of high quality test cases.BS/MS EE, CE or CS
工资范围:
面议
详细待遇:
五险一金,加班补助,绩效奖金,餐补,交通补助,

联系方式

联 系 人：	请投递简历，合则面议。
联系电话：	请投递简历，合则面议。
面试地址：	请投递简历，合则面议。

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