职位详情:

工作地区:	上海	待遇:	面议	学历要求:	高中及以上

岗位要求:
猎头--高级视频算法工程师 职位描述:工作目标：视频编解码方面的算法研发、实现和优化，针对硬件逻辑特点进行算法优化。职位描述：负责视频编解码方面的算法研发和实现，并结合硬件逻辑特点进行算法改进。资历要求：1. 在视频编解码方面有两年以上研发经验，具有扎实的视频编码理论基础；2. 熟悉H.264、HEVC等视频编解码标准，掌握X264、HM等开源代码；3. 有扎实的编程功底，熟练使用C/C++，有软件优化经验；4. 英文熟练，有良好的英语阅读和书面表达能力；5. 硕士以上学历；6. 工作认真负责，严谨细致，有良好的创新意识和团队精神；7. 满足下列条件者之一优先考虑：a) 熟悉HEVC视频编码标准，对HM代码熟练掌握；b) 具有芯片设计相关知识或芯片算法设计经验；c) 具有DSP/ARM等嵌入式平台上算法实现、优化的设计经验；d) 参与HEVC标准制订工作经验。Senior system design engineer Job description:The candidate will be responsible for:l Design and integration an AXI/AHB based system including host processor, DDR controller, SD/MMC, Display I/F and other peripherals., as a verification/demo platform for the in-house designed video IP’s;l Build up the simulation based environment for the system, for the functional verification;l Investigate and develop related drivers for the used IP’s in the system;l Use ISE/Vivado/Quart, implement the design to Altera/Xilinx FPGAs, l Work with SW engineer, to bring up system/OS on the FPGA prototyping board. Debug and resolve failures with Logic Analyzer and/or ChipScope/SignalTap; Qualification:l BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;l Must be highly self-motivator and good team player;l Good understanding and hands-on experiences in SOC development and related methodology;l Solid skills in logic design with Verilog/VHDL, timing closure and analysis;l Familiar with FPGA implementation with ISE/Quartus and debugging;l Knowledge and hands-on experiences in at least 2 of the below fields are required;n AXI/AHB bus protocols;n Design or bring-up of DDR2/3 controller/PHY;n Display interfaces/protocols such as LVDS/HDMI;n SD/MMC controller;n NAND/NOR flush controller； #2. CPU Verification Intern Job description:The candidate will take part in verification for the in-house designed CPU/MCU, including:l Maintain and improve the verification environment and flow;l Make the test plan according to the design specification, and execute it with System verilog based coverage monitors/assertions;l Develop direct tests and constraint random tests;l Coverage data collection and analysis; Qualification:l Graduate student who will graduate in 2015, major in electronic engineering/micro-electronics;l Must be highly self-motivated, eager to learn and accept new knowledge, a quick learner;l Could work at least 4 days every week;l Knowledge and understanding of computer architecture and micro-architecture of RISC processorsl Familiar with front-end ASIC design flow and Verilog HDL;l Familiar or experiences in high-level verification methodology (VMM/UVM/OVM), and/or hardware verification language (SystemC/SystemVerilog) would be a great plus;l Experiences or skills in assembly programming, and using scripting languages (Perl/Tcl/Shell) for flow automation is a plus;
工资范围:
面议
详细待遇:
采暖补贴,补充医疗,五险一金,房补,班车,

联系方式

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联系电话：	请投递简历，合则面议。
面试地址：	请投递简历，合则面议。

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