职位详情:

工作地区:	上海	待遇:	面议	学历要求:	高中及以上

岗位要求:
3个IC职位，分别是两家公司的，大家加油。简历发HR@hi-talent.net urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below. (Sr.) ASIC Design Verification Engineer Position Description: As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including: · Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation; · Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes; · Work with designers to debug failing tests and resolve bugs; · Help develop and maintain flows/scripts/tools for front-end design/verification; Qualification: · BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics; · Self-motivated team player, with strong problem resolving skills; · Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog); · Familiar with video coding standard, and/or computer architecture/micro-architecture; · Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus; · Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation; · Familiar with front-end ASIC design flow; Position: Sr. ASIC Engineer 1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies. 2. IC/IP background. Be interesting in developing and improving New IP. 3. Integration experience, be able to own testchip tapeout. 4. With at least 3-years IP/Product R&D experience. Job Description - RTL coding, new logic design, simulation, synthesis. - Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system. - Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform. - Deliver design/verification/application documents. Qualification and Experience - Very familiar with the Verilog HDL language; - Create the RTL architecture for the algorithm; - Very familiar with C and C++; - Familiar with FPGA tool, ModelSim, and Synplify. - Familiar with the flow of the IC design. Requirements: - Bachelor/Master degree in electronic/computer engineering - Demonstrated abilities in working independently - Strong communication skills Position: ASIC Engineer of SOC and Video system Requirements 1. BS or above in microelectronics, electrical engineering or eq
工资范围:
面议
详细待遇:
包住,带薪年假,保险定期,体检免费,年底双薪,

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