职位详情:

工作地区:	上海	待遇:	面议	学历要求:	高中及以上

岗位要求:
猎头-IC Design engineer/Leader/ManagerIC Design Leader/Manager：Responsibilities: 1.Lead other Design Engineers in a team to meet the companys objectives；2. Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, STA and simulation, chip testing and characterization.3.This is a full-time position with solid equity opportunity. Requirements: 1.5+ years of experience in Verilog/Synthesis-based ASIC Design for mass production IC chipsExperience with project and team management 2.Experience from front-end to back-end (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP) 3.Verilog language and simulation verification experience 4.Logic Synthesis and Static Timing Analysis 5.Interface with Place and Route and back-annotated simulation verification 6.Team-work spirit, and with a strong drive to excelIC Design Engineer：Responsibilities: 1.Work with other Design Engineers to meet the companys objectives；2.Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, simulation and verification, chip testing and characterization. 3.This is a full-time position with solid equity opportunity. Requirements: 1.3+ years of experience in Verilog/Synthesis-based ASIC Design 2.Experience with front to back (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP) 3.Verilog language and simulation verification experience 4.Logic Synthesis and Static Timing Analysis 5.Interface with Place and Route and back-annotated simulation verification 6.Team-work spirit, and with a strong drive to excel智能手机的 数字前端设计经理职位或者engineer集成电路IC设计/应用工程师 职位描述:1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.2. IC/IP background. Be interesting in developing and improving New IP.3. Integration experience, be able to own testchip tapeout.4. With at least 3-years IP/Product R&D experience.Job Description- RTL coding, new logic design, simulation, synthesis.- Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.- Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.- Deliver design/verification/application documents.Qualification and Experience- Very familiar with the Verilog HDL language;- Create the RTL architecture for the algorithm;- Very familiar with C and C++;- Familiar with FPGA tool, ModelSim, and Synplify.- Familiar with the flow of the IC design.Requirements:- Bachelor/Master degree in electronic/computer engineering- Demonstrated abilities in working independently- Strong communication skillsE-Mail:
工资范围:
面议
详细待遇:
餐补,包住,员工旅游,五险一金,采暖补贴,

联系方式

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