职位详情:

工作地区:	上海	待遇:	面议	学历要求:	高中及以上

岗位要求:
Job Title: Senior Design Engineer for Video CodecRole and Chance- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.- Write ASIC specific part of test plan. Co-work with verification engineers to prove functional correctness from block level to SoC level- Support FW/SW bring-up and debugging- Working as the technical point of contact on the ASIC area.- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.Preferred Experience:- Major in EE & CS- Proven ASIC / SoC Design Experience (5+ years as a bachelor, 3+ years as a master).- Must have strong background on IP development- Must be proficient in Verilog coding, debugging and modeling- Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.- Must be skilled in mainstream EDA tools for design and simulation such as ncsim /vcs, RC/DC, PT, Formality/LEC and DFT.- Must be familiar with verification methodologies for from block level to SoC level.- Should be familiar with shell/perl /tcl programming in Linux OS.- Should be familiar with P&R and Manufacture tech.- Good English hearing, speaking, reading and writing capabilities.- Will be a big plus if having mass production tape﹐ut experience.- Will be a plus if having C/C++/SystemVerilog experienceJob Title: Senior Design Verification Engineer for Video CodecRole and ChanceWith increase in ASIC design complexity, design verification becomes an important aspect of the design flow. The candidate will be working in the areas of high speed BUS design and verification for SoC / IP projects. This position requires the candidate to work closely with the ASIC designers on understanding the functional block being designed; compose test plan and validation vectors to ensure functional completeness according to the design specification; apply most advanced verification methodologies to DUT; write BFM model and reference model; and develop and maintain advanced test environments. Preferred Experience:- Bachelor/Master Degree in Electrical or Computer Engineering.- Proven ASIC / SoC Design Verification Experience (5+ years as a bachelor, 3+ years as a master).- Advanced C/C++/SystemVerilog, RTL coding techniques.- PCIe, BIOS, Kernel Driver experience would be an asset.- Design for verification (assertion based design strategies, code coverage, functional coverage,test plan, gate-level simulation, back-annotation etc.)- Hardware emulation, System Performance modeling and analysis- Strong verbal and written communication skills.- Strong problem solving skills.- Ability t
工资范围:
面议
详细待遇:
弹性工作,绩效奖金,加班补助,年底双薪,带薪年假,

联系方式

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